1. Field of the Invention
The invention relates to an electrically modifiable multilevel non-volatile memory having internal refresh means. The invention can be applied especially in the field of memories of large capacities in the range of several tens of megabits.
2. Discussion of Related Art
There are several techniques for increasing the density of memories. One of them consists of the storage of several information bits in a single memory cell. These are then called multilevel memories. The standard memories store one information bit per memory cell, namely one of two programming states. These states correspond to the presence or absence of electrical charges in the floating gates of the transistors constituting the elementary memory cells. The multilevel memories for their part are used to store a greater number of programming states per memory cell.
The patent FR 0 340 107 describes an electrically modifiable non-volatile multilevel memory. Each cell of the memory is capable of storing n possible programming states, with n at least equal to three. These different programming states are obtained by bringing about a variation in the conduction threshold of the floating-gate transistor that forms the memory cell. To obtain this variation of the conduction threshold, the cell is programmed in varying degrees by bringing about a variation of the intensity of the programming, namely either the voltage applied to the cell or the duration of application of the voltage. For the reading of information elements contained in the memory, a current or a voltage that is a function of the programming state of the cell is compared with n-1 reference values in order to deduce therefrom the state of programming of the memory cell among n possible states.
However, the large number of programming states in a multilevel memory and the restricted size of the ranges of voltage or current of these states may then raise problems.
Indeed, it may happen that uncontrolled shifts of electrical charges occur during the operation of programming or erasure of the memory. For example, during the programming of a memory cell of a FLASH EPROM type multilevel memory, a high-voltage Vpp is applied to the word line connected to the control gate of the cell and a lower voltage Vp is applied to the bit line connected to the drain of the cell. The sources of all the cells belonging to the same sector are connected to the ground during the programming. The cells connected to the same word line are then subjected to an electrical field that may be responsible for a shifting of electrical charges and the loss of a programming state if the size of the range of voltage or current of this state is relatively small.
A loss of electrical charges may also occur in read mode at a lower level than in write mode. This does not raise any major problems for a standard memory for the deterioration of the conduction thresholds of the cells is low. However it may be more troublesome for multilevel memories.
To overcome these problems of loss of level, it is indispensable to regularly refresh the memory cells of the multilevel memory.
In a standard way, the operation for refreshing the memory could be performed under the control of a control unit external to the memory. Any access to the memory would then be made impossible during the refresh operation.
Another possible approach would consist of a memory comprising a main matrix of non-volatile memory cells and a secondary matrix of static cells designed to temporarily store data elements of the main matrix. The size of the secondary matrix would, for example, be equal to that of a sector of the main matrix. The refresh operation, which would be done by means internal to the memory, would comprise the following two steps: a step for the duplication of the data elements of a sector of the main matrix in the secondary matrix and a step for the refreshing of the data elements of the duplicated sector of the main matrix. During the refresh step, the data elements of the sector being refreshed would then be accessible in read mode from the secondary matrix. In this exemplary embodiment, the secondary matrix consists of static memory cells in order to minimize the data duplication time.
However, this approach has three major drawbacks:
1. the memory has two different types of memory cells, hence cells of two different technologies in one and the same integrated circuit; this raises problems of cost and manufacture; PA1 2. the data elements to be refreshed undergo a relatively lengthy processing in two steps: a duplication step and a refresh step; and PA1 3. during the refreshing of the memory, the data elements are duplicated in a buffer memory that is volatile. This makes the memory vulnerable to power cuts. PA1 (a) the duplication of the data elements of the sector to be refreshed in the refresh sector; PA1 (b) the modification of the addresses of the data elements of the duplicated sector so that they point to the data elements of the refresh sector; PA1 (c) the erasure of the duplicated sector which becomes the new refresh sector.